CUET Preparation Today
CUET
Physics
Semiconductors and Electronic Devices
The following configuration of gates is equivalent to
NAND
XOR
OR
AND
Out of $G_1=(A+B)$
Output of $G_2=\overline{A.B}$
Output of $G_3=(A+B).\overline{A.B}$
Which gives XOR gate.
