In the diagram, the input is across the terminals A and C and the output is across B and D. Then, the output is:

zero

During the first half cycle when $V_a>V_c$, all the four diodes are forward biased. Hence, no current will flow through $R_L$. During second half cycle when $V_c>V_a$, all the four diodes are reverse biased. Again no current will flow through $R_L$.